In general, in order to estimate a delay of a metal line in a semiconductor device, it is necessary to have information on parameters of the interconnection line, such as capacitance and resistance, and parameters of the interconnection line process, such as width reduction and the thickness of an interlayer dielectric layer.
Conventionally, information on these respective parameters is obtained by using an additional test pattern for extracting information on parameters of an interconnection line for measuring the delay of the interconnection line and information on parameters of the interconnection line process. In this case, since information on the respective parameters may not be extracted in the same environment, there is a problem in that a delay time occurring in an interconnection line may not be precisely estimated.